Ambedkar Institute of Advanced Communication Technologies & Research

Software and Hardware of BCH Coding

Bose, Chaudhuri and Hocquenghem (BCH) codes form a large class of powerful random error-correcting cyclic codes. BCH codes operate over algebraic structures called finite fields and there exist a multitude of decoding algorithms for these codes. Consequently designing BCH codecs is very involved and requires a high level of expertise. This thesis describes the design of the BCH codec synthesis (BCS) system. The BCS system is a design tool that automatically generates the VHDL description of a BCH code given the block length and error correcting ability of the code. These VHDL descriptions are then transported to the gate level using a proprietary synthesis tool. The BCS system is based upon the use of VHDL templates in conjunction with a high level C program. The VHDL templates contain basic knowledge of BCH encoders and decoders and are personalised by the insertion of data calculated by the C program. This data concerns the parameters of the code, the structures of the finite field arithmetic operators and the most appropriate decoding algorithm for the code being considered. Furthermore the C program generates commands files for simulation and a report file and carries out design optimisation.

In the course of this work four new arithmetic circuits operating over finite fields have been developed, a sum of products architecture, a dual-polynomial basis multiplier, a parallel polynomial basis multiplier and a circuit for raising field elements to the third power. These circuits are fast and hardware efficient and have been utilised in the BCS system.

In carrying out design optimisation, the BCS system employs extraction and algorithm selection. Accordingly, different decoding algorithms are used for single, double and triple or more error correcting BCH codes. Triple or more error correcting decoders may also be implemented in two different ways, depending on required hardware/decoding time trade-offs. By these means the developed BCH codes are as hardware efficient as hand-crafted ones but are generated in a fraction of the time

 
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